Advancement to 3,500 nF/mm² Capacitance Density in Silicon Deep Trench Capacitor Technology

ELSPES Inc. has announced a major advancement in its deep trench capacitor (DTC) roadmap with the development of a next-generation silicon capacitor achieving a capacitance density of 3,500 nF/mm². This represents a 40% increase over the company’s earlier 2025 milestone of 2,500 nF/mm², marking the highest density ever produced by ELSPES and further solidifying its leadership in high-performance silicon capacitor technology.

The newly developed capacitor delivers up to 4,300 nF in a compact 1.2 mm × 1.0 mm footprint while maintaining a 4 V breakdown voltage. Despite the increased density, the device continues to provide exceptional electrical performance, including ESR values below 5 mΩ and ESL under 1 pH, ensuring ultra-low impedance across wide frequency ranges. These characteristics make the device particularly well suited for advanced power integrity, high-speed digital, and RF applications where both compact size and stable performance are critical.

ELSPES has also completed design and design-in activities with a U.S.-based customer for commercialization of this technology. The capacitor will be integrated into the customer’s AI chip power delivery network, specifically within its IVR (Integrated Voltage Regulator) core module. Because the IVR is a central component responsible for high-efficiency on-package voltage regulation, the adoption of ELSPES’s silicon capacitor underscores the device’s ability to deliver extremely low impedance, high reliability, and stable operation under fast transient conditions. This collaboration represents a significant step forward in ELSPES’s global engagement and its contribution to next-generation AI computing platforms.

The announcement was featured in Semiconductor Packaging News (SPN) on December 17, 2025, under its Industry Press spotlight, reflecting the market’s growing recognition of ELSPES’s innovation roadmap.